Unit COMPUTER ARCHITECTURE
- Course
- Informatics
- Study-unit Code
- GP004140
- Curriculum
- In all curricula
- Teacher
- Arturo Carpi
- CFU
- 12
- Course Regulation
- Coorte 2019
- Offered
- 2019/20
- Type of study-unit
- Obbligatorio (Required)
- Type of learning activities
- Attività formativa integrata
COMPUTER ARCHITECTURE - MOD. I
| Code | GP004148 |
|---|---|
| CFU | 6 |
| Teacher | Arturo Carpi |
| Teachers |
|
| Hours |
|
| Learning activities | Base |
| Area | Formazione informatica di base |
| Academic discipline | INF/01 |
| Type of study-unit | Obbligatorio (Required) |
| Language of instruction | Italian |
| Contents | Representation of integers. Integer base conversion. Signed integers. Algorithms for addition and subtraction. Binary codes. Logic functions analysis and representation. Implication and coverage. Finding implicants. Non redundant and minimal expressions. A systematic procedure to find minimal forms. The coverage table. Functions non completely specified. Adders, encoders and decoders. The finite state automata. The latches. Reduction of the number of states in a sequential machine. The Moore procedure and the Unger table. The minimal machine. Not completely specified machines. Complexity reduction procedures. Counters and registers. |
| Reference texts | M. Morris Mano, Charles R. Kime, Logic and Computer Design Fundamentals, Pearson F. Barsi, Reti logiche e Trattamento dell'Informazione - Esercizi e verifiche di apprendimento, Margiacchi - Galeno Editrice, Perugia 2010 |
| Educational objectives | The goal of this course is to provide the student with the fundamentals for digital systems study. The main knowledges acquired will concern: Digital information processing, Foundations of Boolean function theory. The course will give to the student the ability of designing elementary logical circuits and analizing their behaviour |
| Prerequisites | In order to attend the course, no special previous knowledge is required, excepted some familiarity with the binary number system and elementary set theory. These notions are commonly known by any student which has a seondary school degree. |
| Teaching methods | Lectures |
| Other information | . |
| Learning verification modality | The final evaluation consists in a written exam. This exam, to be completed in 90 minutes at most, includes the solution of some algorithmic/computational problems as well as the answer to some questions. The goal of this exam is to verify the acquisition of the main theoretical aspect of the discipline and the ability to apply such knowledge in the solution of practical problems. Partial exams (esoneri) will be held during the course. Students who pass these exams will not have to sustain the final exam. Limited to the summer session following the course, students who passed only some of partial exams will be exempted from the corresponding part of the final exam. On student request, exam may be given in English. |
| Extended program | Representation of integers. Integer base conversion. Signed integers. Algorithms for addition and subtraction. Binary codes. Logic functions analysis and representation. Implication and coverage. Finding implicants. Non redundant and minimal expressions. A systematic procedure to find minimal forms. The coverage table. Functions non completely specified. Adders, encoders and decoders. The finite state automata. The latches. Reduction of the number of states in a sequential machine. The Moore procedure and the Unger table. The minimal machine. Not completely specified machines. Complexity reduction procedures. Counters and registers. |
COMPUTER ARCHITECTURE - MOD. II
| Code | GP004149 |
|---|---|
| CFU | 6 |
| Teacher | Alfredo Navarra |
| Teachers |
|
| Hours |
|
| Learning activities | Base |
| Area | Formazione informatica di base |
| Academic discipline | INF/01 |
| Type of study-unit | Obbligatorio (Required) |
| Language of instruction | Italian |
| Contents | Numbers representation: positional, sign-and-magnitude, twos' complement; Designs of adders, multipliers, and dividers; Floating points: 16 bit standard IEEE 754; Cellular automata: Game of Life, Scintillae and Computer architecture; Abstraction levels: Functional level, RTL. Micro-oprerations. Control Unit. Machine cycle. PDP8: register level, functional level, control unit, Assembly. Cache memory. Pipelining |
| Reference texts | 1. F. Barsi: Architettura degli elaboratori, parte seconda: struttura dei sistemi. Margiacchi-Galeno 2. C. Hamacher, Z. Vranesic, S. Zaky, Naraig Manjikian: Introduzione all'architettura dei calcolatori III edizione. McGraw-Hill 3. D. Patterson, J. Hennessy: Struttura e Progetto dei Calcolatori. Zanichelli |
| Educational objectives | Knowledge and understanding about basic properties of a computer, including assembly programming |
| Prerequisites | none |
| Teaching methods | Face-to-face Practical training Seminars |
| Learning verification modality | examination in class |
| Extended program | Numbers representation: positional, sign-and-magnitude, twos' complement; Designs of adders, multipliers, and dividers; Floating points: 16 bit standard IEEE 754; Cellular automata: Game of Life, Scintillae and Computer architecture; Abstraction levels: Functional level, RTL. Micro-oprerations. Control Unit. Machine cycle. PDP8: register level, functional level, control unit, Assembly. Cache memory. Pipelining |